Agentic AI news, research notes, and industry analysis.
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14 stories in this tag.
At Hot Chips 2026 on August 24, Nvidia gave its most detailed technical breakdown of the Vera CPU: 88 Olympus cores on six chiplets, statically partitioned spatial multithreading instead of traditional SMT, a graph prefetcher delivering 3× improvement on graph traversal, and 1.8× on agentic benchmarks over current x86 server CPUs. The design choices reveal what Nvidia thinks "agentic workloads" actually demand from silicon.
Read more →FreeToken, from a team at UC Berkeley and MIT, proposes a serving stack that treats a personal machine's CPU, GPU, and RAM as a single elastic compute surface, adapting to what's actually available rather than committing to a fixed offloading strategy. The result: a 35B model on an 8GB laptop GPU, 284B on a gaming desktop, and the 753B GLM-5.2 on a single workstation with one high-end GPU.
Read more →Cerebras unveiled the CS-4 on August 18 without changing its WSE-3 wafer at all — the gains come from moving power conversion 100× closer to the die and adding a third wafer per rack. The result is a system claiming 4,400 tokens/sec/user, a number that is hard for GPU clusters to match at low batch sizes, along with a 125–135 kW rack TDP that represents the real engineering bet.
Read more →AMD's acquisition of Toronto startup Taalas bets on a structural alternative to GPU-based inference: model-specific integrated circuits that etch weights into mask-ROM on the die itself, eliminating the memory-bandwidth wall that constrains all-general-purpose accelerators. Taalas's HC1 claimed 17,000 tok/s for Llama 3.1 8B at one-tenth the power of an H200. The tradeoff is inflexibility — a finished chip runs exactly one model — but AMD sees a disaggregated future where Taalas handles token generation and Instinct GPUs handle prefill.
Read more →Wafer.ai's benchmarks of Kimi K3 on AMD MI355X tell a story that goes beyond the numbers: the hardware was capable all along, but two ROCm bugs were blocking it. Fixing them yields 48 tok/s per GPU-dollar, against 7 for B200 — a gap that challenges the assumption that NVIDIA owns frontier model inference.
Read more →Meituan's LongCat-2.0 — a 1.6T-parameter open-weight MoE trained entirely on domestic Chinese ASICs — spent two months deployed anonymously on OpenRouter as "Owl Alpha," quietly reaching #1 on Hermes Agent and #2 on Claude Code before the company claimed it. The reveal is technically notable, but the verification gaps are worth keeping in view.
Read more →Meituan open-sourced LongCat-2.0 today — a 1.6-trillion-parameter MoE with a 1M-token context window trained entirely on domestic Huawei Ascend ASICs. It is the first plausible demonstration that frontier-scale pre-training is achievable without NVIDIA hardware, arriving on the same week that US export restrictions on Anthropic's top models remained in partial force.
Read more →Princeton's Kaushik Sengupta describes in IEEE Spectrum how reinforcement learning and electromagnetic emulation have crossed a threshold in radio frequency chip design: AI-generated circuits now routinely outperform human-designed ones, and the layouts look like QR codes — novel topologies that no human designer would produce or easily read.
Read more →Qualcomm agreed to acquire Modular for approximately $3.9 billion on June 24. Modular makes Mojo (a Python-superset systems language) and MAX (a hardware-agnostic inference engine). The deal is a bet that AI inference will fracture across hardware vendors, and whoever owns the abstraction layer wins.
Read more →NVIDIA's RTX Spark puts a Blackwell GPU and full CUDA stack inside a laptop SoC — enough to run a 120B-parameter model locally with 1M-token context. At roughly the same moment, Perplexity shipped a hybrid inference orchestrator that uses a compact on-device model to automatically decide which tasks stay local and which escalate to the cloud. Together they sketch what a local-AI platform actually looks like in hardware and software.
Read more →A detailed engineering account of bringing DeepSeek-V4-Flash up on AMD MI300X reveals the real cost of AMD's software ecosystem gaps: FP8 format fragmentation, missing kernels, and HIP graph constraints that each required dedicated engineering effort before getting to 2,700 tokens/s.
Read more →A project called auto-arch-tournament applies Karpathy's autonomous research loop to RISC-V CPU microarchitecture design: an LLM agent proposes RTL changes, a formal verification pipeline gates acceptance, and 10 winning changes out of 73 proposals deliver a 92% CoreMark improvement in under 10 hours. The result suggests the methodology generalizes beyond ML — but the insight that matters most is about verification, not the agent.
Read more →CERN has been running AI models on FPGAs at the LHC for years, but a Register piece this week described the system in detail. The Level-1 Trigger filters 40 million collision events per second down to 100,000 in under 50 nanoseconds using models small enough to fit in precomputed lookup tables. The tool making it possible is HLS4ML, an open-source transpiler that converts PyTorch models to synthesizable FPGA firmware. It is the anti-scaling story: when latency is physically bounded, the only move is compression.
Read more →Arm's first production AI CPU, Google's TurboQuant, and Hypura's NVMe-first runtime converge on memory bandwidth as the core inference bottleneck.
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