Nvidia has been shipping the Vera CPU in GB300 systems since earlier this year, but Hot Chips 2026 on August 24 was the first time the company broke down the full architectural picture publicly. The ServeTheHome writeup and Tom’s Hardware coverage reveal design choices that tell you what Nvidia thinks agent workloads actually need from a CPU — and where they differ from the assumptions that have shaped server silicon for the last decade.
What the chip is
The Vera CPU has 88 Olympus cores divided across six chiplets (a reticle constraint forced the chiplet approach rather than a monolithic die). The Olympus core is wide: 10-wide decode, deep out-of-order instruction scheduling, neural branch prediction that achieves two taken branches per cycle with zero penalty. These are choices for single-threaded performance — high instructions-per-cycle, not high thread count. The design bet is that agent code paths care more about latency on individual threads than raw parallelism.
Memory bandwidth is 1.2 TB/s via LPDDR5X in a SOCAMM2 package, with the memory subsystem drawing less than 30 W under load. For comparison, DDR5 configurations for server workloads typically exceed 100 W for the memory subsystem alone. Power is a real consideration in dense inference racks; a 70+ W per-socket reduction in memory power is meaningful at scale. A custom graph prefetcher addresses the pointer-chasing access patterns that appear throughout agent memory and knowledge retrieval.
The multithreading decision
The choice that most clearly reveals the design philosophy is the rejection of conventional SMT.
Traditional symmetric multithreading — as used in every major x86 server chip — shares front-end and back-end resources dynamically between threads. When thread A stalls on a cache miss, thread B uses the pipeline. This works when threads have overlapping access patterns that create predictable gaps to fill.
Nvidia chose statically partitioned spatial multithreading instead. Resources are divided at design time. Each thread gets its own static partition of the front-end and back-end; there’s no dynamic sharing. The cost is efficiency loss when one partition sits idle. The benefit is that threads don’t interfere with each other’s working sets.
That tradeoff makes sense for agents. A retrieval operation, a tool call dispatch, and an orchestration loop running concurrently on the same chip have entirely different memory footprints. With dynamic SMT, they’d fight over shared caches and buffers in ways that are hard to predict and harder to optimize. Statically partitioned resources keep each thread’s behavior isolated, which also makes performance more deterministic — an important property when you’re trying to schedule latency-sensitive agent tasks.
Where the 3× graph traversal number comes from
The graph prefetcher is probably the most underexplained part of the Vera architecture. Nvidia claims more than 3× improvement on graph traversal workloads compared to x86 competitors. The use case is direct: agent memory architectures — knowledge graphs, tool dependency graphs, retrieval hierarchies, agent state DAGs — involve extensive pointer-chasing through non-contiguous memory regions.
Standard hardware prefetchers are designed for sequential or stride-based access patterns, which is what matrix operations and traditional database workloads exhibit. A prefetcher that understands graph-like access patterns — following pointer chains, predicting which child nodes will be traversed next — can meaningfully reduce the effective memory latency for agent workloads that spend a significant fraction of their time on retrieval rather than computation.
The overall benchmark
Nvidia reports 1.8× performance on agentic workloads vs. current x86 server CPUs using SPEC CPU 2026 benchmarks, with 1.5× on data processing workloads. These numbers were benchmarked and published at Hot Chips rather than being marketing figures from the launch, which gives them somewhat more credibility.
None of this makes Vera a general inference system replacement. GPU clusters still handle the attention computation and memory-bandwidth-intensive prefill stages; Vera pairs with them via NVLink-C2C. The argument Nvidia is making is narrower: that the orchestration and retrieval layer — the part of an AI serving stack that isn’t a matrix multiply — is worth designing custom silicon for, rather than running on commodity x86 server processors.
Whether that argument holds depends on how much of the overall serving cost is actually spent in that layer. For current agentic deployments that involve a lot of retrieval, tool execution, and context management, the answer may well be “more than you think.”